1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7program t(/*AUTOARG*/); 8 initial begin 9 $write("*-* All Finished *-*\n"); 10 $exit; // Must be in program block 11 end 12endprogram 13