1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2013 by Charlie Brej. 5// SPDX-License-Identifier: CC0-1.0 6 7module submodule (); 8 // This bug only appears when not inlining 9 // verilator no_inline_module 10 initial begin 11 $write("d"); 12 end 13 final begin 14 $write("d"); 15 end 16 final ; // Empty test 17endmodule 18 19module t (); 20 generate 21 for (genvar i = 0; i < 100; i = i + 1) begin : module_set 22 submodule u_submodule(); 23 end 24 endgenerate 25 initial begin 26 $write("*-* All Finished *-*\n"); 27 $finish; 28 end 29endmodule 30