1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2010 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 integer cyc = 0; 14 15 reg [89:0] in; 16 17 /*AUTOWIRE*/ 18 // Beginning of automatic wires (for undeclared instantiated-module outputs) 19 wire [89:0] out; // From test of Test.v 20 wire [44:0] line0; 21 wire [44:0] line1; 22 // End of automatics 23 24 Test test (/*AUTOINST*/ 25 // Outputs 26 .out (out[89:0]), 27 .line0 (line0[44:0]), 28 .line1 (line1[44:0]), 29 // Inputs 30 .clk (clk), 31 .in (in[89:0])); 32 33 // Test loop 34 always @ (posedge clk) begin 35`ifdef TEST_VERBOSE 36 $write("[%0t] cyc==%0d in=%x out=%x\n", $time, cyc, in, out); 37`endif 38 cyc <= cyc + 1; 39 if (cyc==0) begin 40 // Setup 41 in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; 42 end 43 else if (cyc==10) begin 44 if (in==out) begin 45 $write("*-* All Finished *-*\n"); 46 $finish; 47 end 48 else begin 49 $write("*-* Failed!! *-*\n"); 50 $finish; 51 end 52 end 53 end 54 55endmodule 56 57module Test (/*AUTOARG*/ 58 // Outputs 59 line0, line1, out, 60 // Inputs 61 clk, in 62 ); 63 64 input clk; 65 input [89:0] in; 66 67 output reg [44:0] line0; 68 output reg [44:0] line1; 69 output reg [89:0] out; 70 71 assign {line0,line1} = in; 72 always @(posedge clk) begin 73 out <= {line0,line1}; 74 end 75endmodule 76