1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2008 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/);
8
9   // See also t_preproc_kwd.v
10
11   integer bit; initial bit = 1;
12
13   initial begin
14      $write("*-* All Finished *-*\n");
15      $finish;
16   end
17endmodule
18