1%Warning-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. 2 : ... In instance t 3 10 | wire [3:0] foo = 6'h2e; 4 | ^ 5 ... For warning description see https://verilator.org/warn/WIDTH?v=latest 6 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. 7%Error: Exiting due to 8