1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2008 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t;
8
9   // width warnings off due to command line
10   wire A = 15'd1234;
11
12   // width warnings off due to command line + manual switch
13   // verilator lint_off WIDTH
14   wire B = 15'd1234;
15
16   // this turnon does nothing as off on command line
17   // verilator lint_on WIDTH
18   wire C = 15'd1234;
19
20endmodule
21