1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t(/*AUTOARG*/); 8 9 logic never; 10 11 initial begin 12 fork 13 #10; 14 #10; 15 join_none 16 disable fork; 17 wait fork; 18 $write("*-* All Finished *-*\n"); 19 $finish; 20 end 21 22endmodule 23