1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2012 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module init; 8 9 task t1; 10 reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; 11 reg ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz; 12 reg da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn, dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz; 13 begin : READER 14 $display ("Time: %0t Instance: %m", $time); 15 end 16 endtask 17 18 task t2; 19 reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; 20 begin : READER 21 $display ("Time: %0t Instance: %m", $time); 22 end 23 endtask 24endmodule 25 26module test(); 27 init u_ram1(); 28 init u_ram2(); 29endmodule 30