1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2006 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (clk);
8   input clk;
9
10   integer cyc; initial cyc = 0;
11
12   always @(posedge clk) begin
13      cyc <= cyc + 1;
14      if (cyc == 1) begin
15	 ReadContDisps;
16      end
17      else if (cyc == 5) begin
18	 $write("*-* All Finished *-*\n");
19	 $finish;
20      end
21`ifndef verilator
22      DispContDisps;
23`endif
24   end
25
26   task ReadContDisps;
27      begin
28	 $display("%m: Here: %d", cyc);
29      end
30   endtask
31
32   integer dindex;
33
34   task DispContDisps;
35      /* verilator public */
36      begin
37	 if (cyc >= 2) begin
38            if ( cyc >= 4 ) begin
39	       dindex = dindex + 2; //*** Error line
40	       $display("%m: DIndex increment %d", cyc);
41`ifdef VERILATOR
42	       $c("VL_PRINTF(\"Hello1?\\n\");");
43`endif
44            end
45`ifdef VERILATOR
46	    $c("VL_PRINTF(\"Hello2?\\n\");");
47	    $c("VL_PRINTF(\"Hello3?\\n\");");
48`endif
49	 end
50      end
51   endtask
52
53endmodule
54