1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2019 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7function automatic integer min(input integer a, input integer b);
8   return (a < b) ? a : b;
9endfunction
10
11module t
12  #(parameter A=16, parameter B=8)
13   (/*AUTOARG*/
14   // Outputs
15   c,
16   // Inputs
17   a, b
18   );
19
20   input [A-1:0] a;
21   input [B-1:0] b;
22   output logic [min(A,B)-1:0] c;
23
24   always_comb
25     for (int i = 0; i < min(A,B); i++)
26       assign c[i] = a[i] | b[i];
27
28endmodule
29