1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2003-2007 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7`define STRINGIFY(x) `"x`"
8
9module t (/*AUTOARG*/
10   // Inputs
11   clk
12   );
13   input clk;
14   integer 	cyc = 0;
15
16   wire 	out;
17   reg 		in;
18
19   Genit g (.clk(clk), .value(in), .result(out));
20
21   always @ (posedge clk) begin
22      //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out);
23      cyc <= cyc + 1;
24      if (cyc==0) begin
25	 // Setup
26	 in <= 1'b1;
27      end
28      else if (cyc==1) begin
29	 in <= 1'b0;
30      end
31      else if (cyc==2) begin
32	 if (out != 1'b1) $stop;
33      end
34      else if (cyc==3) begin
35	 if (out != 1'b0) $stop;
36      end
37      else if (cyc==9) begin
38	 $write("*-* All Finished *-*\n");
39	 $finish;
40      end
41   end
42
43//`define WAVES
44`ifdef WAVES
45   initial begin
46      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
47      $dumpvars(12, t);
48   end
49`endif
50
51endmodule
52
53module Generate (clk, value, result);
54   input clk;
55   input value;
56   output result;
57
58   reg Internal;
59
60   assign result = Internal ^ clk;
61
62   always @(posedge clk)
63     Internal <= #1 value;
64endmodule
65
66module Checker (clk, value);
67  input clk, value;
68
69   always @(posedge clk) begin
70      $write ("[%0t] value=%h\n", $time, value);
71   end
72
73endmodule
74
75module Test (clk, value, result);
76   input clk;
77   input value;
78   output result;
79
80   Generate gen (clk, value, result);
81   Checker  chk (clk, gen.Internal);
82
83endmodule
84
85module Genit (clk, value, result);
86   input clk;
87   input value;
88   output result;
89
90`ifndef ATSIM  // else unsupported
91 `ifndef NC  // else unsupported
92  `define WITH_FOR_GENVAR
93 `endif
94`endif
95
96`define WITH_GENERATE
97`ifdef WITH_GENERATE
98 `ifndef WITH_FOR_GENVAR
99   genvar i;
100 `endif
101   generate
102      for (
103 `ifdef WITH_FOR_GENVAR
104	   genvar
105 `endif
106	   i = 0; i < 1; i = i + 1)
107	begin : foo
108	   Test tt (clk, value, result);
109	end
110   endgenerate
111`else
112   Test tt (clk, value, result);
113`endif
114
115   wire Result2 = t.g.foo[0].tt.gen.Internal;  // Works - Do not change!
116   always @ (posedge clk) begin
117      $write("[%0t] Result2 = %x\n", $time, Result2);
118   end
119
120endmodule
121