1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2012 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7/* Acceptable answer 1 8created tag with scope = top.t.tag 9created tag with scope = top.t.b.gen[0].tag 10created tag with scope = top.t.b.gen[1].tag 11mod a has scope = top.t 12mod a has tag = top.t.tag 13mod b has scope = top.t.b 14mod b has tag = top.t.tag 15mod c has scope = top.t.b.gen[0].c 16mod c has tag = top.t.b.gen[0].tag 17mod c has scope = top.t.b.gen[1].c 18mod c has tag = top.t.b.gen[1].tag 19*/ 20/* Acceptable answer 2 21created tag with scope = top.t.tag 22created tag with scope = top.t.b.gen[0].tag 23created tag with scope = top.t.b.gen[1].tag 24mod a has scope = top.t 25mod a has tag = top.t.tag 26mod b has scope = top.t.b 27mod b has tag = top.t.tag 28mod c has scope = top.t.b.gen[0].c 29mod c has tag = top.t.tag 30mod c has scope = top.t.b.gen[1].c 31mod c has tag = top.t.tag 32*/ 33 34module t (/*AUTOARG*/ 35 // Inputs 36 clk 37 ); 38 input clk; 39 integer cyc = 0; 40 41 tag tag (); 42 b b (); 43 44 always @ (t.cyc) begin 45 if (t.cyc == 2) $display("mod a has scope = %m"); 46 if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope); 47 end 48 49 always @(posedge clk) begin 50 cyc <= cyc + 1; 51 if (cyc==99) begin 52 $write("*-* All Finished *-*\n"); 53 $finish; 54 end 55 end 56endmodule 57 58module b (); 59 genvar g; 60 generate 61 for (g=0; g<2; g++) begin : gen 62 tag tag (); 63 c c (); 64 end 65 endgenerate 66 always @ (t.cyc) begin 67 if (t.cyc == 3) $display("mod b has scope = %m"); 68 if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope); 69 end 70endmodule 71 72module c (); 73 always @ (t.cyc) begin 74 if (t.cyc == 4) $display("mod c has scope = %m"); 75 if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope); 76 end 77endmodule 78 79module tag (); 80 bit [100*8-1:0] scope; 81 initial begin 82 $sformat(scope,"%m"); 83 $display("created tag with scope = %0s",scope); 84 end 85endmodule 86