1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6// See bug408
7
8module top
9  (
10   output logic [1:0] q,
11   input logic [1:0]  d,
12   input logic        clk
13   );
14
15   genvar             i;
16   assign            q[i] = d[i];
17endmodule
18