1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2003 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 reg _ranit; 13 14 `include "t_initial_inc.vh" 15 16 // surefire lint_off STMINI 17 initial assign user_loaded_value = 1; 18 19 initial _ranit = 0; 20 21 always @ (posedge clk) begin 22 if (!_ranit) begin 23 _ranit <= 1; 24 25 // Test $time 26 // surefire lint_off CWECBB 27 if ($time<20) $write("time<20\n"); 28 // surefire lint_on CWECBB 29 30 // Test $write 31 $write ("[%0t] %m: User loaded ", $time); 32 $display ("%b", user_loaded_value); 33 if (user_loaded_value!=1) $stop; 34 35 // Test $c 36`ifdef VERILATOR 37 $c ("VL_PRINTF(\"Hi From C++\\n\");"); 38`endif 39 user_loaded_value <= 2; 40 41 $write("*-* All Finished *-*\n"); 42 $finish; 43 end 44 end 45 46endmodule 47