1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11   input clk;
12
13   integer cyc; initial cyc = 0;
14   integer a;
15   integer b;
16
17   initial begin
18      a <= 22;
19      b <= 33;
20   end
21
22   always @ (posedge clk) begin
23      cyc <= cyc + 1;
24      if (cyc==99) begin
25         if (a != 22) $stop;
26         if (b != 33) $stop;
27         $write("*-* All Finished *-*\n");
28         $finish;
29      end
30   end
31
32endmodule
33