1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t(/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 localparam int CHECKLIST_P [2:0] = '{0, 1, 2}; 14 15 localparam HIT_LP = 1; 16 localparam MISS_LP = 4; 17 localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; 18 localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; 19 20 initial begin 21 if (HIT_INSIDE != 1) $stop; 22 if (MISS_INSIDE != 0) $stop; 23 end 24 25 integer cyc = 0; 26 27 int array [10]; 28 logic l; 29 30 always @ (posedge clk) begin 31 cyc <= cyc + 1; 32 if (cyc == 0) begin 33 // Setup 34 array[0] = 10; 35 array[1] = 20; 36 array[9] = 90; 37 end 38 else if (cyc < 99) begin 39 l = (10 inside {array}); 40 if (l != 1) $stop; 41 l = (20 inside {array}); 42 if (l != 1) $stop; 43 l = (90 inside {array}); 44 if (l != 1) $stop; 45 l = (99 inside {array}); 46 if (l != 0) $stop; 47 end 48 else if (cyc == 99) begin 49 $write("*-* All Finished *-*\n"); 50 $finish; 51 end 52 end 53 54endmodule 55