1// DESCRIPTION: Verilator: Verilog Test module for Issue#1631
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2019 by Julien Margetts.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   clk
9   );
10   input clk;
11
12   localparam N = 4;
13
14   wire [7:0] cval1[0:N-1];
15   wire [7:0] cval2[N-1:0];
16   wire [7:0] cval3[0:N-1];
17   wire [7:0] cval4[N-1:0];
18
19   wire [3:0] inc;
20
21   assign inc = 4'b0001;
22
23   // verilator lint_off LITENDIAN
24
25   COUNTER UCOUNTER1[N-1:0]
26     (
27      .clk    (clk),
28      .inc    (inc),
29      .o      (cval1) // Twisted
30      );
31
32   COUNTER UCOUNTER2[N-1:0]
33     (
34      .clk    (clk),
35      .inc    (inc),
36      .o      (cval2) // Matches
37      );
38
39   COUNTER UCOUNTER3[0:N-1]
40     (
41      .clk    (clk),
42      .inc    (inc),
43      .o      (cval3) // Matches
44      );
45
46   COUNTER UCOUNTER4[0:N-1]
47     (
48      .clk    (clk),
49      .inc    (inc),
50      .o      (cval4) // Twisted
51      );
52
53   always @(posedge clk) begin
54      if ((cval1[3] != cval2[0]) || (cval3[3] != cval4[0]))
55        $stop;
56
57      if ((cval1[0] + cval1[1] + cval1[2] + cval2[1] + cval2[2] + cval2[3] +
58           cval3[0] + cval3[1] + cval3[2] + cval4[1] + cval4[2] + cval4[3]) != 0)
59        $stop;
60
61`ifdef TEST_VERBOSE
62      $display("%d %d %d %d", cval1[0], cval1[1], cval1[2], cval1[3]);
63      $display("%d %d %d %d", cval2[0], cval2[1], cval2[2], cval2[3]);
64      $display("%d %d %d %d", cval3[0], cval3[1], cval3[2], cval3[3]);
65      $display("%d %d %d %d", cval4[0], cval4[1], cval4[2], cval4[3]);
66`endif
67
68      if (cval1[0] + cval1[3] > 3) begin
69         $write("*-* All Finished *-*\n");
70         $finish;
71      end
72   end
73endmodule
74
75module COUNTER
76  (
77   input            clk,
78   input            inc,
79   output reg [7:0] o
80   );
81
82   initial o = 8'd0;  // No reset input
83
84   always @(posedge clk) if (inc) o <= o + 1;
85
86endmodule
87