1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2003-2007 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 integer cyc; initial cyc=1; 14 15 // verilator lint_on GENCLK 16 reg [31:0] long; 17 reg [63:0] quad; 18 wire [31:0] longout; 19 wire [63:0] quadout; 20 wire [7:0] narrow = long[7:0]; 21 sub sub (/*AUTOINST*/ 22 // Outputs 23 .longout (longout[31:0]), 24 .quadout (quadout[63:0]), 25 // Inputs 26 .narrow (narrow[7:0]), 27 .quad (quad[63:0])); 28 29 always @ (posedge clk) begin 30 if (cyc!=0) begin 31 cyc <= cyc + 1; 32 if (cyc==1) begin 33 long <= 32'h12345678; 34 quad <= 64'h12345678_abcdef12; 35 end 36 if (cyc==2) begin 37 if (longout !== 32'h79) $stop; 38 if (quadout !== 64'h12345678_abcdef13) $stop; 39 $write("*-* All Finished *-*\n"); 40 $finish; 41 end 42 end 43 end 44endmodule 45 46module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout); 47 // verilator public_module 48`ifdef verilator 49 assign longout = $c32("(", narrow, "+1)"); 50 assign quadout = $c64("(", quad, "+1)"); 51`else 52 assign longout = narrow + 8'd1; 53 assign quadout = quad + 64'd1; 54`endif 55endmodule 56