1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2015 by Varun Koyyalagunta. 5// SPDX-License-Identifier: CC0-1.0 6 7// bug1015 8module t (/*AUTOARG*/ 9 // Inputs 10 clk 11 ); 12 input clk; 13 14 integer cyc = 0; 15 reg [63:0] crc; 16 reg [63:0] sum; 17 18 // Take CRC data and apply to testblock inputs 19 wire [1:0] i = crc[1:0]; 20 logic [1:0] o [13:10] ; 21 22 Test test (/*AUTOINST*/ 23 // Outputs 24 .o (o/*[1:0].[3:0]*/), 25 // Inputs 26 .i (i[1:0])); 27 28 // Aggregate outputs into a single result vector 29 wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]}; 30 31 // Test loop 32 always @ (posedge clk) begin 33`ifdef TEST_VERBOSE 34 $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum); 35`endif 36 cyc <= cyc + 1; 37 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 38 sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; 39 if (cyc==0) begin 40 // Setup 41 crc <= 64'h5aef0c8d_d70a4497; 42 sum <= '0; 43 end 44 else if (cyc<10) begin 45 sum <= '0; 46 end 47 else if (cyc<90) begin 48 end 49 else if (cyc==99) begin 50 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); 51 if (crc !== 64'hc77bb9b3784ea091) $stop; 52 // What checksum will we end up with (above print should match) 53`define EXPECTED_SUM 64'hb42b2f48a0a9375a 54 if (sum !== `EXPECTED_SUM) $stop; 55 $write("*-* All Finished *-*\n"); 56 $finish; 57 end 58 end 59 60endmodule 61 62module Test 63 ( 64 output logic [1:0] o [3:0], 65 //but this works 66 //logic [N-1:0] o 67 input [1:0] i); 68 69 parameter N = 4; 70 71 logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3}; 72 73 sub sub [N-1:0] (.o (o), // many-to-many 74 .a (a), // many-to-many 75 .i (i)); // many-to-one 76endmodule 77 78module sub 79 ( 80 input logic [1:0] i, 81 input logic [1:0] a, 82 output logic [1:0] o 83 ); 84 assign o = i + a; 85endmodule 86