1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2010 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13   integer cyc=1;
14
15   counter_io c1_data();
16   counter_io c2_data();
17   //counter_io c3_data;	// IEEE illegal, and VCS doesn't allow non-() as it does with cells
18   counter_io c3_data();
19
20   counter_ansi  c1 (.clkm(clk),
21		     .c_data(c1_data),
22		     .i_value(4'h1));
23   counter_ansi  c2 (.clkm(clk),
24		     .c_data(c2_data),
25		     .i_value(4'h2));
26`ifdef VERILATOR counter_ansi `else counter_nansi `endif
27   /**/ 	 c3 (.clkm(clk),
28		     .c_data(c3_data),
29		     .i_value(4'h3));
30
31   initial begin
32      c1_data.value = 4'h4;
33      c2_data.value = 4'h5;
34      c3_data.value = 4'h6;
35   end
36
37   always @ (posedge clk) begin
38      cyc <= cyc + 1;
39      if (cyc<2) begin
40	 c1_data.reset <= 1;
41	 c2_data.reset <= 1;
42	 c3_data.reset <= 1;
43      end
44      if (cyc==2) begin
45	 c1_data.reset <= 0;
46	 c2_data.reset <= 0;
47	 c3_data.reset <= 0;
48      end
49      if (cyc==3) begin
50	 if (c1_data.get_lcl() != 12345) $stop;
51      end
52      if (cyc==20) begin
53	 $write("[%0t] c1 cyc%0d: c1 %0x %0x  c2 %0x %0x  c3 %0x %0x\n", $time, cyc,
54		c1_data.value, c1_data.reset,
55		c2_data.value, c2_data.reset,
56		c3_data.value, c3_data.reset);
57	 if (c1_data.value != 2) $stop;
58	 if (c2_data.value != 3) $stop;
59	 if (c3_data.value != 4) $stop;
60	 $write("*-* All Finished *-*\n");
61	 $finish;
62      end
63   end
64endmodule
65
66interface counter_io;
67   logic [3:0] value;
68   logic       reset;
69   integer     lcl;
70   task set_lcl (input integer a); lcl=a; endtask
71   function integer get_lcl (); return lcl; endfunction
72endinterface
73
74interface ifunused;
75   logic       unused;
76endinterface
77
78module counter_ansi
79  (
80   input clkm,
81   counter_io c_data,
82   input logic [3:0] i_value
83   );
84
85   initial begin
86      c_data.set_lcl(12345);
87   end
88
89   always @ (posedge clkm) begin
90      c_data.value <= c_data.reset ? i_value : c_data.value + 1;
91   end
92endmodule : counter_ansi
93
94`ifndef VERILATOR
95// non-ansi modports not seen in the wild yet.  Verilog-Perl needs parser improvement too.
96module counter_nansi(clkm, c_data, i_value);
97   input clkm;
98   counter_io c_data;
99   input logic [3:0] i_value;
100
101   always @ (posedge clkm) begin
102      c_data.value <= c_data.reset ? i_value : c_data.value + 1;
103   end
104endmodule : counter_nansi
105`endif
106
107// Test uses Verilator --top-module, which means this isn't in the hierarchy
108// Other simulators will see it, and is illegal to have unconnected interface
109`ifdef VERILATOR
110module modunused (ifunused ifinunused);
111   ifunused ifunused();
112endmodule
113`endif
114