1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty. 5// SPDX-License-Identifier: CC0-1.0 6 7// bug998 8 9module t1(input logic foo); 10 initial begin 11 $display("%m %d", foo); 12 end 13endmodule 14 15module t(); 16 17 logic [1:0] my_foo; 18 19 generate 20 genvar the_genvar; 21 for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf 22 //logic tmp_foo; 23 //assign tmp_foo = my_foo[the_genvar]; 24 t1 t (.foo(my_foo[the_genvar])); 25 //t1 t (.foo(tmp_foo)); 26 end 27 endgenerate 28 29 initial begin 30 $write("*-* All Finished *-*\n"); 31 $finish; 32 end 33endmodule 34