1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2013 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7interface ifc; 8 integer ok; 9 integer bad; 10 modport out_modport (output ok); 11endinterface 12 13module t (/*AUTOARG*/ 14 // Inputs 15 clk 16 ); 17 18 input clk; 19 integer cyc=1; 20 21 ifc itop(); 22 23 counter_ansi c1 (.isub(itop), 24 .i_value(4'h4)); 25 26endmodule 27 28module counter_ansi 29 ( 30 ifc.out_modport isub, 31 input logic [3:0] i_value 32 ); 33 34 always @* begin 35 isub.ok = i_value; 36 isub.bad = i_value; // Illegal access 37 end 38endmodule 39