1// DESCRIPTION: Verilator: Verilog Test module 2// 3// A test of the +verilog2001ext+ and +verilog2005ext+ flags. 4// 5// This source code uses the uwire declaration, which is only valid in Verilog 6// 2005. 7// 8// Compile only test, so no need for "All Finished" output. 9// 10// This file ONLY is placed into the Public Domain, for any use, 11// without warranty, 2012 by Jeremy Bennett. 12// SPDX-License-Identifier: CC0-1.0 13 14module t (/*AUTOARG*/ 15 // Inputs 16 clk 17 ); 18 input clk; 19 20 uwire w; // Only in Verilog 2005 21 22endmodule 23