1// DESCRIPTION: Verilator: Verilog Test module 2// This file ONLY is placed into the Public Domain, for any use, 3// without warranty, 2019 by Todd Strader. 4// SPDX-License-Identifier: CC0-1.0 5 6module secret_impl ( 7 input a, 8 input oe, 9 inout z, 10 output y); 11 12 assign z = oe ? a : 1'bz; 13 assign y = z; 14 15endmodule 16