1%Warning-BLKSEQ: t/t_lint_blksync_bad.v:24:16: Blocking assignments (=) in sequential (flop or latch) block 2 : ... Suggest delayed assignments (<=) 3 24 | sync_blk = 1'b1; 4 | ^ 5 ... For warning description see https://verilator.org/warn/BLKSEQ?v=latest 6 ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. 7%Warning-COMBDLY: t/t_lint_blksync_bad.v:31:18: Delayed assignments (<=) in non-clocked (non flop or latch) block 8 : ... Suggest blocking assignments (=) 9 31 | combo_nblk <= 1'b1; 10 | ^~ 11 *** See https://verilator.org/warn/COMBDLY before disabling this, 12 else you may end up with different sim results. 13%Error: Exiting due to 14