1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2010 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Outputs 9 data_out, 10 // Inputs 11 wr, wa, rst_l, rd, ra, data_in, clk 12 ); 13 input clk; 14 15 /*AUTOINPUT*/ 16 // Beginning of automatic inputs (from unused autoinst inputs) 17 input [31:0] data_in; // To sub of reg_1r1w.v 18 input [7:0] ra; // To sub of reg_1r1w.v 19 input rd; // To sub of reg_1r1w.v 20 input rst_l; // To sub of reg_1r1w.v 21 input [7:0] wa; // To sub of reg_1r1w.v 22 input wr; // To sub of reg_1r1w.v 23 // End of automatics 24 /*AUTOOUTPUT*/ 25 // Beginning of automatic outputs (from unused autoinst outputs) 26 output [31:0] data_out; // From sub of reg_1r1w.v 27 // End of automatics 28 29 reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8)) 30 sub 31 (/*AUTOINST*/ 32 // Outputs 33 .data_out (data_out[31:0]), 34 // Inputs 35 .data_in (data_in[31:0]), 36 .ra (ra[7:0]), 37 .wa (wa[7:0]), 38 .wr (wr), 39 .rd (rd), 40 .clk (clk), 41 .rst_l (rst_l)); 42 43endmodule 44 45module reg_1r1w 46 #( 47 parameter WIDTH=32, 48 parameter ADRWID=10, 49 parameter DEPTH=1024, 50 parameter RST=0 51 ) 52 (/*AUTOARG*/ 53 // Outputs 54 data_out, 55 // Inputs 56 data_in, ra, wa, wr, rd, clk, rst_l 57 ); 58 59 input [WIDTH-1:0] data_in; 60 input [ADRWID-1:0] ra; 61 input [ADRWID-1:0] wa; 62 input wr; 63 input rd; 64 input clk; 65 input rst_l; 66 67 output [WIDTH-1:0] data_out; 68 69 reg [WIDTH-1:0] array [DEPTH-1:0]; 70 reg [ADRWID-1:0] ra_r, wa_r; 71 reg [WIDTH-1:0] data_in_r; 72 reg wr_r; 73 reg rd_r; 74 75 integer x; 76 77 // Message 679 78 always @(posedge clk) begin 79 int tmp = x + 1; 80 if (tmp !== x + 1) $stop; 81 end 82 83 always @(posedge clk or negedge rst_l) begin 84 if (!rst_l) begin 85 for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE 86 if (RST == 1) begin 87 array[x] <= 0; 88 end 89 end 90 ra_r <= 0; 91 wa_r <= 0; 92 wr_r <= 0; 93 rd_r <= 0; 94 data_in_r <= 0; 95 end 96 else begin 97 ra_r <= ra; 98 wa_r <= wa; 99 wr_r <= wr; 100 rd_r <= rd; 101 data_in_r <= data_in; 102 if (wr_r) array[wa_r] <= data_in_r; 103 end 104 end 105endmodule 106 107// Local Variables: 108// verilog-auto-inst-param-value: t 109// End: 110