1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2008 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Outputs
9   q,
10   // Inputs
11   clk, d
12   );
13   input clk;
14   input d;
15   output wire [1:0] q;
16
17   // This demonstrates how warning disables should be propagated across module boundaries.
18
19   m1 m1 (/*AUTOINST*/
20	  // Outputs
21	  .q				(q[1:0]),
22	  // Inputs
23	  .clk				(clk),
24	  .d				(d));
25endmodule
26
27module m1
28  (
29   input clk,
30   input d,
31   output wire [1:0] q
32   );
33
34   m2 m2 (/*AUTOINST*/
35	  // Outputs
36	  .q				(q[1:0]),
37	  // Inputs
38	  .clk				(clk),
39	  .d				(d));
40endmodule
41
42module m2
43  (
44   input clk,
45   input d,
46   // Due to bug the below disable used to be ignored.
47   // verilator lint_off UNOPT
48   // verilator lint_off UNOPTFLAT
49   output reg [1:0] q
50   // verilator lint_on UNOPT
51   // verilator lint_on UNOPTFLAT
52   );
53
54   always @* begin
55      q[1] = d;
56   end
57
58   always @* begin
59      q[0] = q[1];
60   end
61
62endmodule
63