1// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2020 by Julien Margetts.
5
6module t (/*AUTOARG*/ i, o);
7
8   input      [1:0] i;
9   output reg [1:0] o;
10
11    // This should not detect a latch as all options are covered
12   always @* begin
13     if      (i==2'b00) o = 2'b11;
14     else if (i==2'b01) o = 2'b10;
15     else if (i==2'b10) o = 2'b01;
16     else if (i==2'b11) o = 2'b00;
17     else               o = 2'b00; // Without this else a latch is (falsely) detected
18   end
19
20endmodule
21