1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2019 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Outputs
9   rc, rg, ri, rp, rw
10   );
11
12   parameter P = 17;
13   wire [4:0] w = 5'd1;
14
15   output reg [3:0] rc;
16   output reg [3:0] rg;
17   output reg [3:0] ri;
18   output reg [3:0] rp;
19
20   output reg [3:0] rw;
21
22   for (genvar g=16; g < 17; ++g) begin
23      // Index 17 makes a width violation
24      initial begin
25         rg = g;  // WidthMin mismatch
26         rp = P;  // WidthMin mismatch
27         rw = w;  // Always a mismatch
28         rc = 64'h1;  // Always a mismatch (as sized)
29      end
30   end
31   initial begin
32      for (integer i=16; i < 17; ++i) begin
33         ri = i;  // WidthMin mismatch
34      end
35   end
36
37endmodule
38