1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2013. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 integer cyc = 0; 14 reg [63:0] crc; 15 reg [63:0] sum; 16 17 // Take CRC data and apply to testblock inputs 18 wire pick1 = crc[0]; 19 wire [13:0][1:0] data1 = crc[27+1:1]; 20 wire [3:0][2:0][1:0] data2 = crc[23+29:29]; 21 22 /*AUTOWIRE*/ 23 // Beginning of automatic wires (for undeclared instantiated-module outputs) 24 logic [15:0] [1:0] datao; // From test of Test.v 25 // End of automatics 26 27 Test test (/*AUTOINST*/ 28 // Outputs 29 .datao (datao/*[15:0][1:0]*/), 30 // Inputs 31 .pick1 (pick1), 32 .data1 (data1/*[13:0][1:0]*/), 33 .data2 (data2/*[2:0][3:0][1:0]*/)); 34 35 // Aggregate outputs into a single result vector 36 wire [63:0] result = {32'h0, datao}; 37 38 // Test loop 39 always @ (posedge clk) begin 40`ifdef TEST_VERBOSE 41 $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); 42`endif 43 cyc <= cyc + 1; 44 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 45 sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; 46 if (cyc==0) begin 47 // Setup 48 crc <= 64'h5aef0c8d_d70a4497; 49 sum <= 64'h0; 50 end 51 else if (cyc<10) begin 52 sum <= 64'h0; 53 end 54 else if (cyc<90) begin 55 end 56 else if (cyc==99) begin 57 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); 58 if (crc !== 64'hc77bb9b3784ea091) $stop; 59 // What checksum will we end up with (above print should match) 60`define EXPECTED_SUM 64'h3ff4bf0e6407b281 61 if (sum !== `EXPECTED_SUM) $stop; 62 $write("*-* All Finished *-*\n"); 63 $finish; 64 end 65 end 66 67endmodule 68 69module Test 70 ( 71 input logic pick1, 72 input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits 73 input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits 74 output logic [15:0] [1:0] datao // 16 x 2 = 32 bits 75 ); 76 // verilator lint_off WIDTH 77 always_comb datao[13: 0] // 28 bits 78 = (pick1) 79 ? {data1} // 28 bits 80 : {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized 81 // verilator lint_on WIDTH 82 always_comb datao[15:14] = '0; 83endmodule 84