1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2014 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 integer cyc = 0; 14 reg [63:0] crc; 15 reg [63:0] sum; 16 17 // Aggregate outputs into a single result vector 18 //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows 19 wire [3:0] pow4b = crc[7:4] ** crc[3:0]; 20 wire [31:0] pow2 = 2 ** crc[3:0]; // Optimizes to shift 21 wire [63:0] result = {pow2, 28'h0, pow4b}; 22 23 // Test loop 24 always @ (posedge clk) begin 25`ifdef TEST_VERBOSE 26 $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); 27`endif 28 cyc <= cyc + 1; 29 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 30 sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; 31 if (cyc==0) begin 32 // Setup 33 crc <= 64'h5aef0c8d_d70a4497; 34 sum <= 64'h0; 35 end 36 else if (cyc<10) begin 37 sum <= 64'h0; 38 end 39 else if (cyc<90) begin 40 end 41 else if (cyc==99) begin 42 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); 43 if (crc !== 64'hc77bb9b3784ea091) $stop; 44`define EXPECTED_SUM 64'h056ea1c5a63aff6a 45 if (sum !== `EXPECTED_SUM) $stop; 46 $write("*-* All Finished *-*\n"); 47 $finish; 48 end 49 end 50 51endmodule 52