1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2018 by Alex Solomatnikov
5// SPDX-License-Identifier: CC0-1.0
6
7module t;
8   sub #(.REAL(2.0)) sub;
9endmodule
10
11module sub ();
12   parameter REAL = 0.0;
13
14   initial begin
15      $display("REAL %g", REAL);
16      $write("*-* All Finished *-*\n");
17      $finish;
18   end
19endmodule
20