1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2004 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
8
9module t (/*AUTOARG*/
10   // Inputs
11   clk
12   );
13
14   input clk;
15   integer cyc; initial cyc = 0;
16
17   reg [67:0]    r;
18
19   wire and_reduce = &r;
20   wire or_reduce = |r;
21   wire xor_reduce = ^r;
22   wire xnor_reduce = ~^r;
23   wire check_equal = r == 68'hffff_ffff_ffff_ffff_f;
24
25   always @(posedge clk) begin
26`ifdef TEST_VERBOSE
27      $display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x",
28               cyc, r, and_reduce, or_reduce, xor_reduce, check_equal);
29`endif
30      cyc <= cyc + 1;
31      if (cyc == 1) begin
32         r <= 68'd0;
33      end
34      else if (cyc == 10) begin
35         `checkh(r, 68'h0000_0000_0000_0000_0);
36         `checkh(and_reduce, '0);
37         `checkh(or_reduce, '0);
38         `checkh(xor_reduce, '0);
39         `checkh(xnor_reduce, '1);
40         r <= 68'hffff_ffff_ffff_ffff_e;
41      end
42      else if (cyc == 11) begin
43         `checkh(r, 68'hffff_ffff_ffff_ffff_e);
44         `checkh(and_reduce, '0);
45         `checkh(or_reduce, '1);
46         `checkh(xor_reduce, '1);
47         `checkh(xnor_reduce, '0);
48         r <= 68'hffff_ffff_ffff_ffff_f;
49      end
50      else if (cyc == 12) begin
51         `checkh(r, 68'hffff_ffff_ffff_ffff_f);
52         `checkh(and_reduce, '1);
53         `checkh(or_reduce, '1);
54         `checkh(xor_reduce, '0);
55         `checkh(xnor_reduce, '1);
56      end
57      else if (cyc == 90) begin
58         $write("*-* All Finished *-*\n");
59         $finish;
60      end
61      else begin
62         r <= 68'd0;
63      end
64   end
65endmodule
66