1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2004 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Outputs 9 ign, ign2, ign3, ign4, ign4s, 10 // Inputs 11 clk 12 ); 13 14 input clk; 15 output [31:0] ign; 16 output [3:0] ign2; 17 output [11:0] ign3; 18 19 parameter [95:0] P6 = 6; 20 localparam P64 = (1 << P6); 21 22 // verilator lint_off WIDTH 23 localparam [4:0] PBIG23 = 1'b1 << ~73'b0; 24 localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; 25 // verilator lint_on WIDTH 26 27 reg [31:0] iright; 28 reg signed [31:0] irights; 29 reg [31:0] ileft; 30 reg [P64-1:0] qright; 31 reg signed [P64-1:0] qrights; 32 reg [P64-1:0] qleft; 33 reg [95:0] wright; 34 reg signed [95:0] wrights; 35 reg [95:0] wleft; 36 37 reg [31:0] q_iright; 38 reg signed [31:0] q_irights; 39 reg [31:0] q_ileft; 40 reg [P64-1:0] q_qright; 41 reg signed [P64-1:0] q_qrights; 42 reg [P64-1:0] q_qleft; 43 reg [95:0] q_wright; 44 reg signed [95:0] q_wrights; 45 reg [95:0] q_wleft; 46 47 48 reg [31:0] w_iright; 49 reg signed [31:0] w_irights; 50 reg [31:0] w_ileft; 51 reg [P64-1:0] w_qright; 52 reg signed [P64-1:0] w_qrights; 53 reg [P64-1:0] w_qleft; 54 reg [95:0] w_wright; 55 reg signed [95:0] w_wrights; 56 reg [95:0] w_wleft; 57 58 reg [31:0] iamt; 59 reg [63:0] qamt; 60 reg [95:0] wamt; 61 62 assign ign = {31'h0, clk} >>> 4'bx; // bug760 63 assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174 64 assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}}, 65 iamt[1:0] >> {11{iamt[5:2]}}, 66 $signed(iamt[1:0]) >>> {22{iamt[5:2]}}, 67 $signed(iamt[1:0]) >>> {11{iamt[5:2]}}, 68 iamt[1:0] << {22{iamt[5:2]}}, 69 iamt[1:0] << {11{iamt[5:2]}}}; 70 71 wire [95:0] wamtt = {iamt,iamt,iamt}; 72 output wire [95:0] ign4; 73 assign ign4 = wamtt >> {11{iamt[5:2]}}; 74 output wire signed [95:0] ign4s; 75 assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}}; 76 77 always @* begin 78 iright = 32'h819b018a >> iamt; 79 irights = 32'sh819b018a >>> signed'(iamt); 80 ileft = 32'h819b018a << iamt; 81 qright = 64'hf784bf8f_12734089 >> iamt; 82 qrights = 64'shf784bf8f_12734089 >>> signed'(iamt); 83 qleft = 64'hf784bf8f_12734089 << iamt; 84 wright = 96'hf784bf8f_12734089_190abe48 >> iamt; 85 wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt); 86 wleft = 96'hf784bf8f_12734089_190abe48 << iamt; 87 88 q_iright = 32'h819b018a >> qamt; 89 q_irights = 32'sh819b018a >>> signed'(qamt); 90 q_ileft = 32'h819b018a << qamt; 91 q_qright = 64'hf784bf8f_12734089 >> qamt; 92 q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt); 93 q_qleft = 64'hf784bf8f_12734089 << qamt; 94 q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt; 95 q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt); 96 q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt; 97 98 w_iright = 32'h819b018a >> wamt; 99 w_irights = 32'sh819b018a >>> signed'(wamt); 100 w_ileft = 32'h819b018a << wamt; 101 w_qright = 64'hf784bf8f_12734089 >> wamt; 102 w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt); 103 w_qleft = 64'hf784bf8f_12734089 << wamt; 104 w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt; 105 w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt); 106 w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt; 107 end 108 109 integer cyc; initial cyc=1; 110 always @ (posedge clk) begin 111 if (cyc!=0) begin 112 cyc <= cyc + 1; 113`ifdef TEST_VERBOSE 114 $write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright); 115`endif 116 if (cyc==1) begin 117 iamt <= 0; 118 qamt <= 0; 119 wamt <= 0; 120 if (P64 != 64) $stop; 121 if (5'b10110>>2 != 5'b00101) $stop; 122 if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness 123 if (5'b10110<<2 != 5'b11000) $stop; 124 if (5'b10110<<<2 != 5'b11000) $stop; 125 if (5'sb10110>>2 != 5'sb00101) $stop; 126 if (5'sb10110>>>2 != 5'sb11101) $stop; 127 if (5'sb10110<<2 != 5'sb11000) $stop; 128 if (5'sb10110<<<2 != 5'sb11000) $stop; 129 // Allow >64 bit shifts if the shift amount is a constant 130 if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; 131 end 132 if (cyc==2) begin 133 iamt <= 28; 134 qamt <= 28; 135 wamt <= 28; 136 if (ileft != 32'h819b018a) $stop; 137 if (iright != 32'h819b018a) $stop; 138 if (irights != 32'h819b018a) $stop; 139 if (qleft != 64'hf784bf8f_12734089) $stop; 140 if (qright != 64'hf784bf8f_12734089) $stop; 141 if (qrights != 64'hf784bf8f_12734089) $stop; 142 if (wleft != 96'hf784bf8f12734089190abe48) $stop; 143 if (wright != 96'hf784bf8f12734089190abe48) $stop; 144 if (wrights != 96'hf784bf8f12734089190abe48) $stop; 145 end 146 if (cyc==3) begin 147 iamt <= 31; 148 qamt <= 31; 149 wamt <= 31; 150 if (ileft != 32'ha0000000) $stop; 151 if (iright != 32'h8) $stop; 152 if (irights != 32'hfffffff8) $stop; 153 if (qleft != 64'hf127340890000000) $stop; 154 if (qright != 64'h0000000f784bf8f1) $stop; 155 if (qrights != 64'hffffffff784bf8f1) $stop; 156 if (wleft != 96'hf12734089190abe480000000) $stop; 157 if (wright != 96'h0000000f784bf8f127340891) $stop; 158 if (wrights != 96'hffffffff784bf8f127340891) $stop; 159 end 160 if (cyc==4) begin 161 iamt <= 32; 162 qamt <= 32; 163 wamt <= 32; 164 if (ileft != 32'h0) $stop; 165 if (iright != 32'h1) $stop; 166 if (qleft != 64'h8939a04480000000) $stop; 167 if (qright != 64'h00000001ef097f1e) $stop; 168 end 169 if (cyc==5) begin 170 iamt <= 33; 171 qamt <= 33; 172 wamt <= 33; 173 if (ileft != 32'h0) $stop; 174 if (iright != 32'h0) $stop; 175 if (qleft != 64'h1273408900000000) $stop; 176 if (qright != 64'h00000000f784bf8f) $stop; 177 end 178 if (cyc==6) begin 179 iamt <= 64; 180 qamt <= 64; 181 wamt <= 64; 182 if (ileft != 32'h0) $stop; 183 if (iright != 32'h0) $stop; 184 if (qleft != 64'h24e6811200000000) $stop; 185 if (qright != 64'h000000007bc25fc7) $stop; 186 end 187 if (cyc==7) begin 188 iamt <= 128; 189 qamt <= 128; 190 wamt <= 128; 191 if (ileft != 32'h0) $stop; 192 if (iright != 32'h0) $stop; 193 if (qleft != 64'h0) $stop; 194 if (qright != 64'h0) $stop; 195 end 196 if (cyc==8) begin 197 iamt <= 100; 198 qamt <= {32'h10, 32'h0}; 199 wamt <= {32'h10, 64'h0}; 200 if (ileft != '0) $stop; 201 if (iright != '0) $stop; 202 if (irights != '1) $stop; 203 if (qleft != '0) $stop; 204 if (qright != '0) $stop; 205 if (qrights != '1) $stop; 206 if (wleft != '0) $stop; 207 if (wright != '0) $stop; 208 if (wrights != '1) $stop; 209 end 210 if (cyc==19) begin 211 $write("*-* All Finished *-*\n"); 212 $finish; 213 end 214 215 // General rule to test all q's 216 if (cyc != 0) begin 217 if (ileft != q_ileft) $stop; 218 if (iright != q_iright) $stop; 219 if (irights != q_irights) $stop; 220 if (qleft != q_qleft) $stop; 221 if (qright != q_qright) $stop; 222 if (qrights != q_qrights) $stop; 223 if (wleft != q_wleft) $stop; 224 if (wright != q_wright) $stop; 225 if (wrights != q_wrights) $stop; 226 227 if (ileft != w_ileft) $stop; 228 if (iright != w_iright) $stop; 229 if (irights != w_irights) $stop; 230 if (qleft != w_qleft) $stop; 231 if (qright != w_qright) $stop; 232 if (qrights != w_qrights) $stop; 233 if (wleft != w_wleft) $stop; 234 if (wright != w_wright) $stop; 235 if (wrights != w_wrights) $stop; 236 end 237 end 238 end 239endmodule 240