1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2011 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6//
7// bug354
8
9typedef logic [5:0]  data_t;
10
11module t (/*AUTOARG*/
12   // Inputs
13   clk
14   );
15   input clk;
16
17   integer 	cyc = 0;
18   reg [63:0] 	crc;
19   reg [63:0] 	sum;
20
21   // Take CRC data and apply to testblock inputs
22   wire 	rst;
23   data_t 	iii_in = crc[5:0];
24   data_t 	jjj_in = crc[11:6];
25   data_t	iii_out;
26   data_t	jjj_out;
27   logic [1:0]	ctl0 = crc[63:62];
28
29   aaa aaa (.*);
30
31   // Aggregate outputs into a single result vector
32   wire [63:0] result = {64'h0};
33
34   // Test loop
35   always @ (posedge clk) begin
36`ifdef TEST_VERBOSE
37      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
38`endif
39      cyc <= cyc + 1;
40      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
41      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
42      if (cyc==0) begin
43	 // Setup
44	 crc <= 64'h5aef0c8d_d70a4497;
45	 sum <= 64'h0;
46	 rst <= 1'b0;
47      end
48      else if (cyc<10) begin
49	 sum <= 64'h0;
50	 rst <= 1'b1;
51      end
52      else if (cyc<90) begin
53	 rst <= 1'b0;
54      end
55      else if (cyc==99) begin
56	 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
57	 if (crc !== 64'hc77bb9b3784ea091) $stop;
58	 // What checksum will we end up with (above print should match)
59`define EXPECTED_SUM 64'h4afe43fb79d7b71e
60	 if (sum !== `EXPECTED_SUM) $stop;
61	 $write("*-* All Finished *-*\n");
62	 $finish;
63      end
64   end
65
66endmodule
67
68module bbb
69   (
70    output data_t   ggg_out[1:0],
71    input data_t    ggg_in [1:0],
72    input [1:0] [1:0] ctl,
73
74    input logic    clk,
75    input logic    rst
76    );
77
78   genvar 	   i;
79
80   generate
81      for (i=0; i<2; i++) begin: PPP
82	 always_ff @(posedge clk) begin
83	    if (rst) begin
84	       ggg_out[i] <= 6'b0;
85	    end
86	    else begin
87	       if (ctl[i][0]) begin
88		  if (ctl[i][1]) begin
89		     ggg_out[i] <= ~ggg_in[i];
90		  end else begin
91		     ggg_out[i] <= ggg_in[i];
92		  end
93	       end
94	    end
95	 end
96      end
97   endgenerate
98
99endmodule
100
101module aaa
102   (
103    input  data_t iii_in,
104    input  data_t jjj_in,
105    input  [1:0] ctl0,
106    output data_t iii_out,
107    output data_t jjj_out,
108    input  logic clk,
109    input  logic rst
110    );
111
112   // Below is a bug; {} concat isn't used to make arrays
113  bbb bbb (
114	   .ggg_in  ({jjj_in,            iii_in}),
115	   .ggg_out ({jjj_out,           iii_out}),
116	   .ctl	    ({{1'b1,ctl0[1]},    {1'b0,ctl0[0]}}),
117           .*);
118
119endmodule
120