1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2005 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11   input clk;
12   integer cyc; initial cyc=1;
13
14   // verilator lint_off LATCH
15   // verilator lint_off UNOPT
16   // verilator lint_off UNOPTFLAT
17   // verilator lint_off MULTIDRIVEN
18   // verilator lint_off BLKANDNBLK
19
20   reg [31:0] comcnt;
21   reg [31:0] dlycnt;  initial dlycnt=0;
22   reg [31:0] lastdlycnt; initial lastdlycnt = 0;
23
24   reg [31:0] comrun;  initial comrun = 0;
25   reg [31:0] comrunm1;
26   reg [31:0] dlyrun;  initial dlyrun = 0;
27   reg [31:0] dlyrunm1;
28   always @ (posedge clk) begin
29      $write("[%0t] cyc %d\n", $time,cyc);
30      cyc <= cyc + 1;
31      if (cyc==2) begin
32	 // Test # of iters
33	 lastdlycnt = 0;
34	 comcnt = 0;
35	 dlycnt <= 0;
36      end
37      if (cyc==3) begin
38	 dlyrun <= 5;
39	 dlycnt <= 0;
40      end
41      if (cyc==4) begin
42	 comrun = 4;
43      end
44   end
45   always @ (negedge clk) begin
46      if (cyc==5) begin
47	 $display("%d %d\n", dlycnt, comcnt);
48	 if (dlycnt != 32'd5) $stop;
49	 if (comcnt != 32'd19) $stop;
50	 $write("*-* All Finished *-*\n");
51	 $finish;
52      end
53   end
54
55   // This forms a "loop" where we keep going through the always till comrun=0
56   reg runclk;  initial runclk = 1'b0;
57   always @ (/*AS*/comrunm1 or dlycnt) begin
58      if (lastdlycnt != dlycnt) begin
59	 comrun = 3;
60	 $write ("[%0t] comrun=%0d start\n", $time, comrun);
61      end
62      else if (comrun > 0) begin
63	 comrun = comrunm1;
64	 if (comrunm1==1) begin
65	    runclk = 1;
66	    $write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun);
67	 end
68	 else $write ("[%0t] comrun=%0d\n", $time, comrun);
69      end
70      lastdlycnt = dlycnt;
71   end
72
73   always @ (/*AS*/comrun) begin
74      if (comrun!=0) begin
75	 comrunm1 = comrun - 32'd1;
76	 comcnt = comcnt + 32'd1;
77	 $write("[%0t]                comcnt=%0d\n", $time,comcnt);
78      end
79   end
80
81   // This forms a "loop" where we keep going through the always till dlyrun=0
82   reg runclkrst;
83   always @ (posedge runclk) begin
84      runclkrst <= 1;
85      $write ("[%0t] runclk\n", $time);
86      if (dlyrun > 0) begin
87	 dlyrun <= dlyrun - 32'd1;
88	 dlycnt <= dlycnt + 32'd1;
89	 $write ("[%0t]   dlyrun<=%0d\n", $time, dlyrun-32'd1);
90      end
91   end
92
93   always @* begin
94      if (runclkrst) begin
95	 $write ("[%0t] runclk reset\n", $time);
96	 runclkrst = 0;
97	 runclk = 0;
98      end
99   end
100
101endmodule
102