1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Anderson Ignacio da Silva. 5// SPDX-License-Identifier: CC0-1.0 6 7package test_pkg; 8 localparam [31:0] test_arr [4][4:0] 9 = '{ 10 '{'h0000, 'h1000, 'h2000, 'h3000, 'h4000}, 11 '{'h0FFF, 'h1FFF, 'h2FFF, 'h3FFF, 'h4FFF}, 12 '{ 'd0, 'd0, 'd0, 'd0, 'd0}, 13 '{ 'd0, 'd1, 'd2, 'd3, 'd4} 14 }; 15 16 typedef struct packed{ 17 logic [7:0] val_1; 18 logic [7:0] val_2; 19 } test_ret_t; 20endpackage 21 22module t import test_pkg::*; (clk); 23 input clk; 24 25 function automatic test_ret_t test_f(logic [31:0] val); 26 test_ret_t temp; 27 28 temp = test_ret_t'(0); 29 for (int i=0; i<5; i++) begin 30 if (val >= test_arr[0][i] && val <= test_arr[1][i]) begin 31 temp.val_1 = test_arr[2][i][7:0]; 32 temp.val_2 = test_arr[3][i][7:0]; 33 end 34 end 35 return temp; 36 endfunction 37 38 test_ret_t temp; 39 logic [31:0] random; 40 41 int cyc; 42 bit [63:0] sum; 43 44 always @ (posedge clk) begin 45 cyc <= cyc + 1; 46 random <= {17'b0, cyc[3:0], 11'b0}; 47 temp <= test_f(random); 48`ifdef TEST_VERBOSE 49 $display("rand: %h / Values -> val_1: %d / val_2: %d", random, temp.val_1, temp.val_2); 50`endif 51 if (cyc > 10 && cyc < 90) begin 52 sum <= {48'h0, temp} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; 53 end 54 else if (cyc == 99) begin 55 $displayh(sum); 56 if (sum != 64'h74d34ea7a775f994) $stop; 57 $write("*-* All Finished *-*\n"); 58 $finish; 59 end 60 end 61endmodule 62