1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2013 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/);
8
9    function integer max2;
10       input integer x;
11       input integer y;
12       begin
13	  begin : blk
14	     automatic int temp;
15	     temp = x;
16	  end
17       end
18       max2 = ( x > y ) ? x : y;
19    endfunction
20
21    function integer max4;
22       input integer x;
23       input integer y;
24       input integer z;
25       input integer w;
26       // MAX2 is used multiple times
27       max4 = max2( max2( x, y ), max2( z, w ) );
28    endfunction
29
30   localparam  MAX4 = max4( 1, 1, 0, 0 );
31
32   initial begin
33      if (MAX4 != 1) $stop;
34      $write("*-* All Finished *-*\n");
35      $finish;
36   end
37endmodule
38