1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t; 8 sub #(.WIDTH(4)) sub4(); 9 sub #(.WIDTH(8)) sub8(); 10 11 logic [3:0] out4; 12 logic [7:0] out8; 13 14 initial begin 15 out4 = sub4.orer(4'b1000); 16 out8 = sub8.orer(8'b10000000); 17 if (out4 != 4'b1011) $stop; 18 if (out8 != 8'b10111111) $stop; 19 out4 = sub4.orer2(4'b1000); 20 out8 = sub8.orer2(8'b10000000); 21 if (out4 != 4'b1001) $stop; 22 if (out8 != 8'b10011111) $stop; 23 $write("*-* All Finished *-*\n"); 24 $finish; 25 end 26endmodule 27 28 29module sub; 30 parameter WIDTH = 1; 31 32 function [WIDTH-1:0] orer; 33 input [WIDTH-1:0] in; 34 // IEEE provices no way to override this parameter, basically it's a localparam 35 parameter MASK_W = WIDTH - 2; 36 localparam [MASK_W-1:0] MASK = '1; 37 // verilator lint_off WIDTH 38 return in | MASK; 39 // verilator lint_on WIDTH 40 endfunction 41 42 function [WIDTH-1:0] orer2; 43 input [WIDTH-1:0] in; 44 // Same param names as other function to check we disambiguate 45 // IEEE provices no way to override this parameter, basically it's a localparam 46 parameter MASK_W = WIDTH - 3; 47 localparam [MASK_W-1:0] MASK = '1; 48 // verilator lint_off WIDTH 49 return in | MASK; 50 // verilator lint_on WIDTH 51 endfunction 52endmodule 53