1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7//bug505
8
9module t (/*AUTOARG*/
10   // Inputs
11   clk
12   );
13   input clk;
14
15   parameter TOP_PARAM /*verilator public*/ = 20;
16
17   a #(1) a1 ();
18   b #(2) b2 ();
19
20   initial begin
21      $write("*-* All Finished *-*\n");
22      $finish;
23   end
24endmodule
25
26module a;
27   parameter ONE /*verilator public*/ = 22;
28   initial if (ONE != 1) $stop;
29`ifdef VERILATOR
30   initial if ($c32("this->ONE") != 1) $stop;
31`endif
32endmodule
33
34module b #(
35	   parameter TWO /*verilator public*/ = 22
36	   );
37   initial if (TWO != 2) $stop;
38`ifdef VERILATOR
39   initial if ($c32("this->TWO") != 2) $stop;
40`endif
41endmodule
42
43//bug804
44package p;
45   localparam INPACK /*verilator public*/ = 6;
46endpackage
47