1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2005 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 parameter [31:0] TWENTY4 = 24; 14 parameter [31:0] PA = TWENTY4/8; 15 parameter [1:0] VALUE = 2'b10; 16 parameter [5:0] REPL = {PA{VALUE}}; 17 parameter [7:0] CONC = {REPL,VALUE}; 18 19 parameter DBITS = 32; 20 parameter INIT_BYTE = 8'h1F; 21 parameter DWORDS_LOG2 = 7; 22 parameter DWORDS = (1<<DWORDS_LOG2); 23 parameter DBYTES=DBITS/8; 24 // verilator lint_off LITENDIAN 25 reg [DBITS-1:0] mem [0:DWORDS-1]; 26 // verilator lint_on LITENDIAN 27 28 integer i; 29 30 integer cyc=1; 31 always @ (posedge clk) begin 32 cyc <= cyc + 1; 33 if (cyc==1) begin 34 if (REPL != {2'b10,2'b10,2'b10}) $stop; 35 if (CONC != {2'b10,2'b10,2'b10,2'b10}) $stop; 36 end 37 if (cyc==2) begin 38 for (i = 0; i < DWORDS; i = i + 1) 39 mem[i] = {DBYTES{INIT_BYTE}}; 40 end 41 if (cyc==3) begin 42 for (i = 0; i < DWORDS; i = i + 1) 43 if (mem[i] != {DBYTES{INIT_BYTE}}) $stop; 44 end 45 if (cyc==9) begin 46 $write("*-* All Finished *-*\n"); 47 $finish; 48 end 49 end 50 51endmodule 52