1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2021 by Geza Lore. 5// SPDX-License-Identifier: CC0-1.0 6 7module t(/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 wire o0, o1; 14 15 sub #(1) a(.i(1'b0), .o(o0)); 16 sub #(2) b(.i(1'b0), .o(o1)); 17 18 always @(posedge clk) begin 19 if (o0 != 1'b0) begin 20 $write("Bad o0\n"); 21 $stop; 22 end 23 if (o1 != 1'b1) begin 24 $write("Bad o1\n"); 25 $stop; 26 end 27 $write("*-* All Finished *-*\n"); 28 $finish; 29 end 30 31endmodule 32 33module sub 34 #( 35 parameter int W 36 ) 37 ( 38 input wire i, 39 output wire o 40 ); 41 42 typedef struct packed { 43 logic [W-1:0] a; 44 } s; 45 46 sub2 #(s) c(.i(i), .o(o)); 47 48endmodule 49 50module sub2 51 # ( 52 parameter type T = logic 53 ) 54 ( 55 input wire i, 56 output wire o 57 ); 58 59 if ($bits(T) % 2 == 1) begin 60 assign o = i; 61 end else begin 62 assign o = ~i; 63 end 64 65endmodule 66