1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2018 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 d, clk, num 10 ); 11 input d; 12 input clk; 13 input int num; 14 15 always @ (posedge clk) begin 16 if ($past(d, num)) $stop; // IEEE 16.9.3 must be const 17 if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >= 0 18 if ($past(d, 10000)) $stop; // TICKCOUNT 19 end 20endmodule 21