1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2009 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7`undefineall 8 9// Definitions as speced 10// Note there are trailing spaces, which spec doesn't show properly 11`define D(x,y) initial $display("start", x , y, "end"); 12'`D( "msg1" , "msg2" )' 13'initial $display("start", "msg1" , "msg2" , "end");' 14'`D( " msg1", )' 15'initial $display("start", " msg1" , , "end");' 16'`D(, "msg2 ")' 17'initial $display("start", , "msg2 ", "end");' 18'`D(,)' 19'initial $display("start", , , "end");' 20'`D( , )' 21'initial $display("start", , , "end");' 22//`D("msg1") // ILLEGAL: only one argument 23//`D() // ILLEGAL: only one empty argument 24//`D(,,) // ILLEGAL: more actual than formal arguments 25 26// Defaults: 27`define MACRO1(a=5,b="B",c) $display(a,,b,,c); 28'`MACRO1 ( , 2, 3 )' 29'$display(5,,2,,3);' 30'`MACRO1 ( 1 , , 3 )' 31'$display(1 ,,"B",,3 );' 32'`MACRO1 ( , 2, )' 33'$display(5,,2,,);' 34//`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c 35 36`define MACRO2(a=5, b, c="C") $display(a,,b,,c); 37'`MACRO2 (1, , 3)' 38'$display(5,,,,"C");' 39'`MACRO2 (, 2, )' 40'$display(5,,2,,"C");' 41'`MACRO2 (, 2)' 42'$display(5,,2,,"C");' 43 44`define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); 45'`MACRO3 ( 1 )' 46'$display(1 ,,0,,"C");' 47'`MACRO3 ( )' 48'$display(5,,0,,"C");' 49//`MACRO3 // ILLEGAL: parentheses required 50 51`define DTOP(a,b) a + b 52'`DTOP( `DTOP(b,1), `DTOP(42,a) )' 53'b + 1 + 42 + a' 54 55// Local tests 56`define MACROQUOTE(a="==)",b="((((",c=() ) 'a b c' 57`MACROQUOTE(); 58'"==)" "((((" () '; 59 60// Also check our line counting doesn't go bad 61`define MACROPAREN(a=(6), 62 b=(eq=al), 63 c) 'a b c' 64`MACROPAREN( 65 66 67 68 ,, 69 70 71 ZOT) 72HERE-`__LINE__ - Line71 73 74//====================================================================== 75