1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2019 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7class Cls; 8 randc int i; 9 10 function new; 11 i = 0; 12 endfunction 13 14endclass 15 16module t (/*AUTOARG*/); 17 bit ok = 0; 18 19 Cls obj; 20 21 initial begin 22 int rand_result; 23 int prev_i; 24 for (int i = 0; i < 10; i++) begin 25 obj = new; 26 rand_result = obj.randomize(); 27 if (i > 0 && obj.i != prev_i) begin 28 ok = 1; 29 end 30 prev_i = obj.i; 31 end 32 if (ok) begin 33 $write("*-* All Finished *-*\n"); 34 $finish; 35 end 36 else $stop; 37 end 38endmodule 39