1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2008 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/);
8
9   reg [72:1] in;
10   initial begin
11      if (in[(   (1'h0 / 1'b0)   )+:71] != 71'h0) $stop;
12   end
13
14endmodule
15