1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/);
8
9   typedef struct packed { bit m; } struct_t;
10   struct_t s;
11
12   initial begin
13      s.nfmember = 0; // Member not found
14      $finish;
15   end
16endmodule
17