1// DESCRIPTION: Verilator: Large test for SystemVerilog
2
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2012.
5// SPDX-License-Identifier: CC0-1.0
6
7// Contributed by M W Lund, Atmel Corporation.
8
9module adrdec
10 #( parameter
11      NSLAVES  = 2 )
12 (
13  // ***************************************************************************
14  // Module Interface (interfaces, outputs, and inputs)
15  // ***************************************************************************
16
17  // **** Interfaces ****
18  genbus_if.adrdec dbus
19
20 );
21
22  // ***************************************************************************
23  // Address Decode
24  // ***************************************************************************
25
26//  const logic [15:0] adrmap[1:2] = '{}
27
28  always_comb
29    begin
30      logic sel [1:NSLAVES];
31      sel[1] = (dbus.s_adr[1][7:4] == 4'h0);
32      sel[2] = (dbus.s_adr[2][7:4] == 4'h1);
33//      sel[3] = (dbus.s_adr[3][7:4] == 4'h2);
34
35      dbus.s_sel = sel;
36//      for ( i = 1; i <= dbus.aNumSlaves; i++ )
37//        begin
38//          dbus.s_sel[i] = (dbus.s_adr[i] == adrmap[i]);
39//        end
40    end
41
42endmodule // adrdec
43