1// DESCRIPTION: Verilator: Large test for SystemVerilog
2
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2012.
5// SPDX-License-Identifier: CC0-1.0
6
7// Contributed by M W Lund, Atmel Corporation.
8
9typedef struct packed
10               {
11                 bit [1:0] size;
12               } mPreAdrDecode_resp;
13
14
15interface genbus_if
16 #( parameter
17      DSIZE    = 2,
18      SSIZE    = DSIZE,
19      ASIZE    = 16,
20      NMASTERS = 1,
21      NSLAVES  = 1,
22      DMSB     = (DSIZE<<3) - 1,
23      SMSB     = SSIZE - 1,
24      AMSB     = ASIZE - 1
25  )
26 (
27  // **** Inputs ****
28
29  // - System -
30  input  logic        clk,              // Device Clock.
31  input  logic        rst,              // Device Reset.
32  input  logic        test_mode         // Test mode.
33 );
34
35  // ***************************************************************************
36  // Interface Variables
37  // ***************************************************************************
38
39  // **** Master ****
40  logic [DMSB:0] m_sdata[1:NMASTERS];   // Slave data.
41  logic          m_ws   [1:NMASTERS];   // Slave wait state.
42  logic [DMSB:0] m_mdata[1:NMASTERS];   // Master data.
43  logic [AMSB:0] m_adr  [1:NMASTERS];   // Address.
44  logic [SMSB:0] m_we   [1:NMASTERS];   // Write enable.
45  logic [SMSB:0] m_re   [1:NMASTERS];   // Read enable.
46
47
48  // **** Slave ****
49  logic [DMSB:0] s_sdata[1:NSLAVES];    // Slave data       (from slave).
50  logic          s_ws   [1:NSLAVES];    // Slave wait state (from slave).
51  logic [DMSB:0] s_mdata[1:NSLAVES];    // Master data      (to slave).
52  logic [AMSB:0] s_adr  [1:NSLAVES];    // Address          (to slave).
53  logic [SMSB:0] s_we   [1:NSLAVES];    // Write enable     (to slave).
54  logic [SMSB:0] s_re   [1:NSLAVES];    // Read enable      (to slave).
55
56
57  // **** Address Decoder ****
58  logic          s_sel  [1:NSLAVES];    // Slave select (to slave).
59
60
61
62  // ***************************************************************************
63  // Modports
64  // ***************************************************************************
65
66  modport master(
67                  import mConnect,
68                  import mPreAdrDecode,
69                  input  m_sdata,
70                  input  m_ws,
71                  output m_mdata,
72                  output m_adr,
73                  output m_we,
74                  output m_re
75                 );
76
77  // - Slaves -
78  modport slave(
79                 import sConnect,
80                 output s_sdata,
81                 output s_ws,
82                 input  s_mdata,
83                 input  s_adr,
84                 input  s_we,
85                 input  s_re,
86                 input  s_sel
87                );
88
89// UNSUPPORTED
90//  for (genvar i = 1; i <= NSLAVES; i++ )
91//    begin: mps
92//      modport slave(
93//                    import sConnect,
94//                    output .s_sdata( s_sdata[i] ),
95//                    output .s_ws   ( s_ws   [i] ),
96//                    input  .s_mdata( s_mdata[i] ),
97//                    input  .s_adr  ( s_adr  [i] ),
98//                    input  .s_we   ( s_we   [i] ),
99//                    input  .s_re   ( s_re   [i] ),
100//                    input  .s_sel  ( s_sel  [i] )
101//                    );
102//    end
103
104//   blocks
105
106  modport adrdec(
107                  import aNumSlaves,
108                  input  s_adr,
109                  output s_sel
110                 );
111
112
113
114  // ***************************************************************************
115  // Bus Multiplexers
116  // ***************************************************************************
117
118  always_comb
119    begin: busmux
120      // - Local Variables -
121      integer i;
122
123      // - Defautls -
124      m_sdata[1] = {(DSIZE<<3){1'b0}};
125      m_ws   [1] = 1'b0;
126
127      for ( i = 1; i <= NSLAVES; i++ )
128        begin
129          m_sdata[1] |= s_sdata[i];
130          m_ws   [1] |= s_ws   [i];
131
132          s_mdata[i]  = m_mdata[1];
133          s_adr  [i]  = m_adr  [1];
134          s_we   [i]  = m_we   [1];
135          s_re   [i]  = m_re   [1];
136        end
137    end
138
139
140
141  // ***************************************************************************
142  // Master Functions and Tasks
143  // ***************************************************************************
144
145  function automatic void mConnect( input  integer          id,
146                                    output logic   [DMSB:0] sdata,
147                                    output logic            ws,
148                                    input  logic   [DMSB:0] mdata,
149                                    input  logic   [AMSB:0] adr,
150                                    input  logic   [SMSB:0] we,
151                                    input  logic   [SMSB:0] re  );
152    begin
153      m_mdata[id] = mdata;
154      m_adr  [id] = adr;
155      m_we   [id] = we;
156      m_re   [id] = re;
157
158      sdata = m_sdata[id];
159      ws    = m_ws   [id];
160    end
161  endfunction
162
163
164  function automatic mPreAdrDecode_resp mPreAdrDecode( input  integer          id,
165                                                       input  logic   [AMSB:0] adr );
166    begin
167      // ToDo: Add parameterized address decoding!!!!
168
169      // Example code:
170      if ( adr[0] )
171        mPreAdrDecode.size = 2'b01;   // Word (16-bit) memory.
172      else
173        mPreAdrDecode.size = 2'b10;   // Double Word (32-bit) memory.
174    end
175  endfunction
176
177
178
179  // ***************************************************************************
180  // Slave Functions and Tasks
181  // ***************************************************************************
182
183  function automatic void sConnect( input  integer          id,
184                                    input  logic            rst,
185                                    input  logic   [DMSB:0] sdata,
186                                    input  logic            ws,
187                                    output logic   [DMSB:0] mdata,
188                                    output logic   [AMSB:0] adr,
189                                    output logic   [SMSB:0] we,
190                                    output logic   [SMSB:0] re );
191    begin
192      s_sdata[id] = sdata & {(DSIZE<<3){s_sel[id]}};
193      // verilator lint_off WIDTH
194      s_ws   [id] = ws & {SSIZE{s_sel[id]}};
195      // verilator lint_on WIDTH
196
197      mdata  = s_mdata[id] & {16{~rst}};
198      adr    = s_adr  [id];
199      we     = (s_we   [id] & {SSIZE{s_sel[id]}}) | {SSIZE{rst}};
200      re     = s_re   [id] & {SSIZE{s_sel[id]}};
201    end
202  endfunction
203
204
205
206  // ***************************************************************************
207  // Address Decoder Functions and Tasks
208  // ***************************************************************************
209
210
211  function automatic integer aNumSlaves;
212     aNumSlaves = NSLAVES;
213  endfunction
214
215endinterface // genbus_if
216