1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2008 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7`include "verilated.v" 8 9`define STRINGIFY(x) `"x`" 10 11module t; 12 integer infile, outfile; 13 integer count, a; 14 15 initial begin 16 infile = $fopen("t/t_sys_file_scan_input.dat", "r"); 17 outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_scan_test.log"}, "w"); 18 19 count = 1234; 20`ifdef TEST_VERBOSE 21 $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); 22`endif 23 count = $fscanf(infile, "%d\n", a); 24`ifdef TEST_VERBOSE 25 // Ifdefing this out gave bug248 26 $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); 27`endif 28 if (count == 0) $stop; 29 $fwrite(outfile, "# a\n"); 30 $fwrite(outfile, "%d\n", a); 31 $fclose(infile); 32 $fclose(outfile); 33 34 $write("*-* All Finished *-*\n"); 35 $finish(0); // Test arguments to finish 36 end 37 38endmodule 39